教师名录
崔爱娇
通讯地址:哈尔滨工业大学深圳研究生院C栋
电子邮件:cuiaj@hit.edu.cn
联系电话:

研究方向

1. 集成电路硬件安全技术
2. 集成电路测试技术
3. 印刷电子设计
4. 忆阻器设计及应用

欢迎对集成电路设计、硬件安全及集成电路测试等研究课题感兴趣的同学报考研究生!

教育经历

2005-2009  获哲学博士学位(电子工程),新加坡南洋理工大学
学位论文:保护集成电路知识产权的基于约束的水印技术研究
2000-2003  获工学硕士学位(电子工程),北京师范大学
学位论文:基于NTP协议的授时系统研究
1996-2000  获工学学士学位(通信与信息系统),北京师范大学
学位论文:基于GPS和广播的授时系统

研究与工作经历

2016至今  副教授,硕导,哈工大深研院电子与信息工程学院
2010-2016  助理教授,硕导,哈工大深研院电子与信息工程学院
2009-2010  研究人员,北京大学深圳SOC重点实验室
2003-2004  教师,北京交通大学电信工程学院
  
  

专业资质与学术兼职

2005至今  IEEE 会员
2010至今  CCF会员
2011至今  IEEE Transactions on VLSI Large Scale Integration Systems 评审人
2016至今  IEEE Transactions on Circuits and Systems,IEEE Transactions on Computer-aided design for integrated circuits, IEEE Transactions on information forensics and security 评审人
2012至今   Integration, the VLSI Journal评审人
2012至今  Microelectronics Journal评审人
2012至今  国家自然科学基金和浙江省自然科学基金评审人
2016至今  中国电子设计自动化会议(ChinaEDA)程序委员会委员
2017  AsianHost 会议 publication chair
2017  ICCD会议程序执行委员
2017  ATS会议session chair
2018  AsinaHost 会议程序执行委员

科研项目

2017-2020  国家自然科学基金面上项目 加密芯片抗扫描旁路攻击的关键技术研究 主持
2011-2013  国家自然科学基金青年项目 用于VLSI IP保护的现场可检测混合动态水印技术研究 主持
2016-2019  广东省自然科学基金面上项目 密码芯片的安全可测试性设计技术研究 主持
2013-2015  教育部留学人员科研启动基金 保护大规模集成电路知识产权的动态水印技术研究
主持
2018-2019  计算机体系结构国家重点实验室开放课题 主持
2016-2018  深圳市海外高层次人才创新项目 主持
2015-2017  深圳市基础研究项目 主持
2013-2015  深圳市基础研究项目 主持
2012-2014  深圳市基础研究项目 主持
2010-2012  深圳市基础研究项目 主持
2009-2010  深圳市基础研究项目 主持
2012-2013  哈工大创新项目 主持
2011-2011  横向项目 主持

科研成果及奖励

2015  深圳市后备级人才
2015  哈工大教学优秀奖
2014  深圳海外高层次C类人才孔雀计划
2014  哈工大青年教师研究生课程教学竞赛二等奖
2014  哈工大深研院教学竞赛一等奖

论文及著作

[8] Aijiao Cui*, Y. Luo and C. H. Chang,"Static and dynamic obfuscation of scan data against scan-based side-channel attacks" IEEE Transactions on Information Forensics and Security, vol. 12, no. 2, Feb. 2017, pp. 363-376. (SCI检索, 影响因子4.332, JCR 1区, CCF-A类期刊)

[7] Aijiao Cui*, Yanhui Luo, Huawei Li, Gang Qu,"Why current secure scan design fail and how to fix them" Integration, the VLSI Journal, 56 (2017), pp. 105-114. (SCI检索,影响因子0.703,JCR3区,CCF-C类期刊)

[6] Aijiao Cui*, G. Qu and Y. Zhang,"Ultra-low overhead dynamic watermarking on scan design for hard IP protection" IEEE Transactions on Information Forensics and Security, vol.10, no.11, July 2015, pp. 2298-2313. (SCI检索, 影响因子4.332, JCR 1区, CCF-A类期刊)

[5] L. Chen, Aijiao Cui* and C. H. Chang,"Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction" IEEE Transactions on Computers, vol. 64, no. 12, Feb. 2015, pp. 3417-3492. (SCI检索, 影响因子2.916, JCR 1区, CCF-A类期刊 )

[4] R. Sun, Y. Zhang and A. Cui,"a refined affine approximation method of multiplication for range analysis in word-length optimization" Eurasip Journal on Advances in Signal Processing, March 2014, article 36. (SCI检索,影响因子0.928, JCR 3区)

[3] Aijiao Cui*, C. H. Chang and S. Tahar, “A robust FSM watermarking scheme for IP protection of sequential circuit design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,vol. 30, no. 5, May 2011, pp. 678-690. (SCI检索,影响因子1.942, JCR 2区,CCF-A类期刊)

[2] C. H. Chang and Aijiao Cui, “Synthesis-for-Testability watermarking for field authentication of VLSI intellectual property,” IEEE Trans. on Circuits and Systems I, vol. 57, no. 7, August 2010,pp. 1618-1630.(SCI检索,影响因子2.407, JCR 1区)

[1] Aijiao Cui, C. H. Chang and S. Tahar, “IP watermarking using incremental technology mapping at logic synthesis level,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 9, Sept. 2008, pp. 1565-1570. (SCI检索,影响因子1.942, JCR 2区,CCF-A类期刊)


[1] 侯建军,佟毅,崔爱娇,曾涛,数字电路实验一体化教程(2003年高等教育百门精品课程教材建设立项项目),清华大学出版社、北京交通大学出版社,2007年1月。

会议论文及发表演说

[25] Wenxuan Wang, Aijiao Cui*, Gang Qu, Huawei Li, “A Low-overhead PUF based on Parallel Scan Design” in Proceedings Asia and South Pacific Design Automation Conference ASP-DAC 2018, Jan. 2018, pp. 715-720. (CCF-C类会议)

[24] Wei Zhou, Aijiao Cui*, Huawei Li, Gang Qu, “How to secure scan design against scan-based side-channel attacks?” in proceedings IEEE Asian Test Symposium, Nov. 2017, invited paper, pp. 121-126. (CCF-C类会议)

[23] Aijiao Cui*, Xuesen Qian, Gang Qu, Huawei Li, “A New Active IC metering Technique based on Locking Scan Cells” In proceedings IEEE Asian Test Symposium, Nov. 2017, pp. 40-45. (CCF-C类会议)

[22] Xiaonan Huang, Aijiao Cui*, Chip Hong Chang," A New Watermarking Scheme on Scan Chain Ordering for Hard IP Protection" in Proceedings IEEE International Symposium on Circuits and Systems, May 2017, pp. 1-4. (CCF-C类会议)

[21] X. Chen, G. Qu, Aijiao Cui, "Practical IP watermarking and fingerprinting methods for ASIC designs" 2017 IEEE International Symposium on Circuits and Systems (ISCAS), May 2017, pp: 1-4.(CCF-C类会议)

[20] X. Chen, G. Qu, Aijiao Cui, C. Dunbar, "Scan chain based IP fingerprint and identification" in 2017 18th International Symposium on Quality Electronic Design (ISQED), 2017, pp: 264 - 270.

[19] Jiadong Wang, Aijiao Cui*, Mengyang Li, Gang Qu and Huawei Li,"An ultra-low overhead LUT-based PUF for FPGA" in Proceedings IEEE Asian HOST, Dec. 2016, pp. 1-6.

[18] Yanhui Luo, Aijiao Cui*, G. Qu and Huawei Li," A new countermeasure against scan-based side-channel attacks," in Proceedings IEEE International Symposium on Circuits and Systems, May 2016, pp. 1722-1725. (CCF-C类会议)

[17] Lucheng He, Aijiao Cui*," An improved test power optimization method by insertion of linear function," in Proceedings IEEE International Symposium on Circuits and Systems, May 2016, pp. 2631-2634. (CCF-C类会议)

[16] Aijiao Cui, T. Yu, M. Li and G. Qu,"A scan design method based on two complementary connection styles to minimize Test power" in Proceedings IEEE International Symposium on Circuits and Systems, May 2015, pp. 625-628. (CCF-C类会议)

[15] Aijiao Cui, T. Yu, G. Qu and M. Li,"An improved scan design for minimization of test power under routing constraint" in Proceedings IEEE International Symposium on Circuits and Systems, May 2015, pp. 629-632. (CCF-C类会议)

[14] T. Yu, Aijiao Cui, M. Li, A. Ivanov,"A new decompressor with ordered parallel scan design for reduction of test data and test time" in Proceedings IEEE International Symposium on Circuits and Systems, May 2015, pp. 641-644. (CCF-C类会议)

[13] M. Gao, K. Lai, J. Zhang, G. Qu, Aijiao Cui, Q. Zhou ,"Reliable and anti-cloning PUFs based on configurable ring oscillators" in International conference on computer-aided design and computer graphics, April 2015, pp. 194-201.

[12] M. Li, Aijiao Cui and T. Yu,"An Improved Scan Cell Ordering Method Using the Scan Cells with Complementary Outputs" in Proceedings 14th International Symposium on Integrated Circuits, Dec. 2014, pp. 103-106.

[11] T. Yu, Aijiao Cui and M. Li, "A new scan ordering method for test power optimization under routing constraint" in IEEE 15th Workshop on RTL and High Level Testing, Nov. 2014.

[10] Aijiao Cui, W. Liang and G. Qu,"A low-overhead dynamic watermarking scheme on scan design for easy authentication" in Proceedings IEEE International Symposium on Circuits and Systems, June 2014, Melbourne, Australia, pp. 778-781. (CCF-C类会议)

[9] Y. Liu, Aijiao Cui,"An efficient zero-aliasing space compactor based on elementary gates" on proceedings of 2013 13th International Conference on Computer-Aided Design and Computer Graphics, Hongkong, Nov. 2013, pp. 95-100.

[8] L. Chen and Aijiao Cui, “A power-efficient scan tree design by exploring the Q'-D connection,” in Proceedings IEEE International Symposium on Circuits and Systems, Beijing, China, May 2013, pp. 1018-1021. (CCF-C类会议)

[7] Aijiao Cui, and C. H. Chang, “A Post-processing scan-chain watermarking scheme for VLSI intellectual property protection” in Proceedings IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, Taiwan, pp. 412-415, Dec. 2012.

[6] Aijiao Cui, C. H. Chang and L. Zhang, “A hybrid watermarking scheme for sequential functions,” in Proceedings IEEE International Symposium on Circuits and Systems, Rio. Brazil, pp. 2333-2336, May 2011. (CCF-C类会议)

[5] Aijiao Cui and C. H. Chang, “An improved publicly detectable watermarking scheme
based on scan chain ordering,” Proc. IEEE Int. Symp. on Circuits and Syst., Taipei, May 2009, pp. 29-32. (CCF-C类会议)

[4] Aijiao Cui and C. H. Chang, “Intellectual property authentication by watermarking scan chain in design-for-testability flow,” Proc. IEEE Int. Symp. on Circuits and Syst., Seattle, USA, May 2008, pp. 2645-2648. (CCF-C类会议)

[3] Aijiao Cui and C. H. Chang, “Watermarking for IP Protection through Template Substitution at Logic Synthesis Level,” Proc. IEEE Int. Symp. on Circuits and Syst., New Orleans, USA, May 2007, pp. 3687-3690. (CCF-C类会议)

[2] Aijiao Cui and C. H. Chang, “Kernel Extraction for Watermarking Combinational Logic Networks,” Proceedings IEEE Asia Pacific Conference on Circuits and Systems, Singapore, December 2006, pp. 1023-1026.

[1] Aijiao Cui and C. H. Chang, “Stego-signature at logic synthesis level for digital design IP protection,” Proceedings IEEE International Symposium on circuits and Systems, Kos, Greece, May 2006, pp. 4611-4614. (CCF-C类会议)

任教和任导师经历

哈工大深圳研究生院电子与信息工程学院  【1】陈林枫,硕士研究生,2011至2013,本科毕业于沈阳工业大学;

*硕士毕业论文:Research of Scan Tree Design for the reduction of test time and test power. 答辩成绩全学科排名1/23,被评为2013哈尔滨工业大学优秀毕业生,毕业论文被评为“哈工大优秀硕士毕业论文”(学科唯一);

*发表SCI (JCR 1区, 影响因子1.659)文章一篇,EI检索文章一篇。硕士期间受资助赴北京参加国际会议并作报告。

*目前工作于华为公司(深圳)集成电路测试。

【2】刘永霞,硕士研究生,2011至2013,本科毕业于哈尔滨理工大学;

*硕士毕业论文:Research of dynamic watermarking techniques for VLSI IP protection. 答辩成绩全学科排名2/23;

*发表EI检索文章一篇。硕士期间受资助赴香港参加国际会议并作报告。

*目前工作于华为公司(北京)数字电路设计。

【3】于婷婷,硕士研究生,2012至2014,本科毕业于哈尔滨理工大学;

*硕士毕业论文:Research of optimization for test power, test time and test data volume in scan chain design. 答辩成绩全学科排名1/24; 被评为2014哈尔滨工业大学优秀毕业生,毕业论文被评为“哈工大优秀硕士毕业论文”(学科唯一)。

*发表EI检索文章4篇,workshop文章1篇。硕士期间受资助赴新加坡和杭州参加国际会议并作报告。

*目前工作于华为公司(深圳)数字电路设计。

【4】骆彦辉,硕士研究生,2013至2015,本科毕业于天津理工大学;

*硕士毕业论文:Research of secure scan designs against scan-based side-channel attacks. 毕业论文成绩全学科排名1/25; 被评为2015哈尔滨工业大学优秀毕业生,毕业论文被评为“哈工大优秀硕士毕业论文”(学科唯一)。

*发表EI检索文章2篇, JCR 1 区文章1篇,JCR3区文章1篇。硕士期间受资助赴上海参加学术会议并作报告。

*目前工作于超微半导体(AMD)公司(上海)数字电路设计。

【5】何禄成,硕士研究生,2013至2015,本科毕业于中南大学;

研究课题:Research of scan design techniques for the optimization of test power.毕业论文成绩全学科排名2/25; 被评为2015哈尔滨工业大学优秀毕业生。

*发表EI检索文章1篇。硕士期间受资助赴上海参加学术会议。

【6】李孟扬,硕士研究生,2014-2016,本科毕业于长春理工大学;

研究课题:Study of secure design-for-testability technique based on cryptographic hash function.毕业论文成绩全学科排名1/28; 被评为2016哈尔滨工业大学优秀毕业生,毕业论文被评为“哈工大优秀硕士毕业论文”(学科唯一)。

*发表EI一作文章1篇,一篇SCI文章在评审中。硕士期间受资助赴葡萄牙里斯本参加ISCAS2015学术会议。

*目前工作于华为(深圳)。


【7】王佳东,硕士研究生,2014-2016,本科毕业哈尔滨理工大学;

研究课题:Research on design and application of delay-based physical unclonable function.

*发表EI一作文章1篇。硕士期间受资助赴台湾参加2015AsianHost学术会议。

*目前工作于中兴(深圳)。

【8】黄晓男,硕士研究生,2014-2016,本科毕业哈尔滨工业大学;

研究课题:Study of design for testability based IP watermarking techniques.

*发表EI一作文章1篇。

【9】王文煊,硕士研究生,2015-2017,本科毕业河南大学;

研究课题:Study on design and application of delay-based physical unclonable function based on parallel scan chain. 毕业论文成绩全学科排名1/29; 被评为2017哈尔滨工业大学优秀毕业生,毕业论文被评为“哈工大优秀硕士毕业论文”(学科唯一)。

*发表EI一作文章1篇。硕士期间受资助赴韩国台湾参加2018AspDac学术会议。

*目前工作于华为(深圳)。

【10】钱学森,硕士研究生,2015-2017,本科毕业于哈尔滨工程大学;

研究课题:Study of Active IC Metering for Anti-Counterfeit. 毕业论文成绩全学科排名3/29;

*发表EI二作文章1篇。硕士期间受资助赴台湾参加2017ATS学术会议。

*目前工作于联发软件设计(深圳)有限公司
最后更新:2018-03-23 14:19:59